1. Field of the Invention
The present invention relates to an EEPROM (electrically erasable programmable read-only memory) device having an array of memory cells composed of nonvolatile data-storage elements.
2. Description of the Prior Art
An EEPROM device achieves the erasing and writing of data electrically by injecting and ejecting electrons to and from floating gates. To achieve this, an EEPROM device exploits the current that is caused to flow through an oxide film or the like by the tunnel effect when a high-level voltage is applied to the oxide film. However, applying a uniform writing time to every individual EEPROM device leads to the problem described below because of the considerably large variations in the characteristics of EEPROM devices that cannot be avoided in their manufacturing process (note that, in the present specification, a "writing time" signifies the length of time required to complete a cycle of erasing and writing operations in a memory cell).
Specifically, a long writing time causes, in memory cells that exhibit good electron injection and ejection characteristics, an increase in the rate at which electrons are injected and ejected. This leads to the dielectric breakdown of tunnel oxide films and thus to the degradation of their characteristics. However, in memory cells that are poor in the above-mentioned characteristics, a long writing time allows data to be written securely and thus leads to an increased yield of EEPROM devices. By contrast, a short writing time leads, in memory cells that are good in the above-mentioned characteristics, to an increased yield but, in memory cells that are poor in the above-mentioned characteristics, to data errors due to insufficient electron injection and ejection.
To overcome this problem, some conventional EEPROM devices are designed to use a variable writing time. An example of such EEPROM devices is proposed, for example, in Japanese patent No. 2,510,521. In this conventional EEPROM device, a clock generated by an oscillation circuit is divided by a frequency divider into a plurality of reference signals divided in different ratios, and the writing time is varied by selecting a different one of these reference signals.
However, in this conventional EEPROM device, it is impractical to increase the number of reference signals above a certain limit, and therefore the writing time can be varied only in a limited number of steps. Moreover, to make the selection of the frequency-division ratio possible, it is necessary to provide, separately from the memory cell array, a data-storage element dedicated to the storage of data related to the frequency-division ratio. This necessitates the use of, for example, a polyfuse and thus leads to a larger chip area, because the polyfuse requires sufficient extra space to place position indication marks that are referred to when the polyfuse is cut with a laser beam and to prevent the effect of the cutting on the portion around the polyfuse.